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HT24LC32 CMOS 32K 2-Wire Serial EEPROM
Features
* Operating voltage: 2.4V~5.5V * Low power consumption - Operation: 5mA max. - Standby: 5mA max. * Internal organization: 40968 * 2-wire Serial Interface * Write operation with built-in timer * Write cycle time: 5ms max. * 32-byte Page Write Mode * Partial page write allowed * Hardware controlled write protection * Automatic erase-before-write operation * 106 rewrite cycles per word * 40-year data retention * Commercial temperature range (0C to +70C) * 8-pin DIP/SOP/TSSOP package
General Description
The HT24LC32 is a 32K-bit 2-wire serial read/write non-volatile memory device using the CMOS floating gate process. Its 32768 bits of memory are organized into 4096 words and 8 bits per word. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The HT24LC32 has high reliability endurance of 1M erase/write cycles and 40-year data retention.
Block Diagram
SCL SDA I/O C o n tro l L o g ic X D WP M e m o ry C o n tro l L o g ic E C P a g e B u ffe r YDEC A0~A2 VCC VSS A d d re s s C o u n te r S ense A M P R /W C o n tro l EEPROM A rra y
Pin Assignment
A0 1 8 2 7 3 6 4 5 VCC WP SCL SDA
HV Pum p
A1 A2 VSS
H T24LC32 8 D IP -A /S O P -A /T S S O P -A
Pin Description
Pin Name A0~A2 SDA SCL WP VSS VCC I/O I I/O I I 3/4 3/4 Address input Serial data Serial clock input Write protect Negative power supply, ground Positive power supply Description
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Absolute Maximum Ratings
Applied VCC Voltage with Respect to VSS .................................................................................VSS -0.3V to VSS+6.0V Applied Voltage on any Pin with Respect to VSS ................................................................................................VSS -0.3V to VCC+0.3V Operating Temperature (Commercial) ........................................................................................................ 0C to 70C Storage Temperature ............................................................................................................................ -50C to 125C Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VCC ICC1 ICC2 VIL VIH VOL ILI ILO ISTB1 ISTB2 CIN COUT Parameter Operating Voltage Operating Current Operating Current Input Low Voltage Input High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Standby Current Standby Current Input Capacitance (See Note) Test Conditions VCC 3/4 5V 5V 3/4 3/4 Conditions 3/4 Read at 100kHz Write at 100kHz 3/4 3/4 Min. 2.4 3/4 3/4 -1 0.7VCC 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
Ta=0C to 70C Max. 5.5 2 5 0.3VCC VCC+0.5 0.4 1 1 5 4 6 8 Unit V mA mA V V V mA mA mA mA pF pF
2.4V IOL=2.1mA 5V 5V 5V VIN=0 or VCC VOUT=0 or VCC VIN=0 or VCC
2.4V VIN=0 or VCC 3/4 f=1MHz 25C f=1MHz 25C
Output Capacitance (See Note) 3/4
Note: These parameters are periodically sampled but not 100% tested.
A.C. Characteristics
Symbol fSK tHIGH tLOW tR tF tHD:STA tSU:STA Parameter Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time START Condition Setup Time Note Note After this period, the first clock pulse is generated. Only relevant for repeated START condition. 3/4 3/4 3/4 3/4 Remark 3/4 3/4 3/4 Standard Mode* Min. 3/4 4000 4700 3/4 3/4 4000 4000 0 200 4000 3/4 Max. 100 3/4 3/4 1000 300 3/4 3/4 3/4 3/4 3/4 3500 Min. 3/4 600 1200 3/4 3/4 600 600 0 100 600 3/4
Ta=0C to 70C VCC=5V10% Max. 400 3/4 3/4 300 300 3/4 3/4 3/4 3/4 3/4 900 Unit kHz ns ns ns ns ns ns ns ns ns ns
tHD:DAT Data Input Hold Time tSU:DAT Data Input Setup Time
tSU:STO STOP Condition Setup Time tAA Output Valid from Clock
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Symbol Parameter Remark Time in which the bus must be free before a new transmission can start Noise suppression time 3/4 Standard Mode* Min. 4700 Max. 3/4 VCC=5V10% Min. 1200 Max. 3/4 Unit
tBUF
Bus Free Time Input Filter Time Constant (SDA and SCL Pins) Write Cycle Time
ns
tSP tWR Note:
3/4 3/4
100 5
3/4 3/4
50 5
ns ms
These parameters are periodically sampled but not 100% tested * The standard mode means VCC=2.4V to 5.5V For relative timing, refer to timing diagrams
Functional Description
* Serial clock (SCL)
The SCL input is used for positive edge clock data into each EEPROM device and negative edge clock data out of each device.
* Serial data (SDA)
stable whenever the clock line is high. Changes in data line while the clock line is high will be interpreted as a START or STOP condition.
* Start condition
The SDA pin is bidirectional for serial data transfer. The pin is open drain driven and may be wired-OR with any number of other open drain or open collector devices.
* A0, A1, A2
A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition Timing diagram).
* Stop condition
The A2, A1 and A0 pins are device address inputs that are hard wired or left not connected for hardware compatibility with HT24LC32. When the pins are hardwired, as many as eight 32K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). These inputs must be tied to VCC or VSS, to establish the device select code.
* Write protect (WP)
A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram).
* Acknowledge
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
D a ta a llo w e d to c h a n g e SDA
The HT24LC32 has a write protect pin that provides hardware data protection. The write protect pin allows normal read/write operations when the connection is grounded. When the write protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following table. WP Pin Status At VCC At VSS (floating) Protect Array Full array (32K) Normal read/write operations
SCL S ta rt c o n d itio n A d d re s s o r a c k n o w le d g e v a lid NoACK s ta te
S to p c o n d itio n
Device Addressing The 32K EEPROM devices require an 8-bit device address word following a start condition to enable the chip for a read or write operation. The device address word consist of a mandatory one, zero sequence for the first four most significant bits (refer to the diagram showing the Device Address). This is common to all the EEPROM device. The 32K EEPROM uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins.
Memory Organization Internally organized with 4096 8-bit words, the 32K requires a 12-bit data word address for random word addressing. Device Operations
* Clock and data transition
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain
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The 8th bit device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. If the comparison of the device address succeed the EEPROM will output a zero at ACK bit. If not, the chip will return to a standby state.
1 0 1 0 A2 A1 A0 R /W
D e v ic e A d d r e s s
The data word address lower 5 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the data word address will roll over and previous data will be overwritten.
* Acknowledge polling
Device Address Write Operations
* Byte write
A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. After receiving the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle to the nonvolatile memory. All inputs are disabled during this write cycle and EEPROM will not respond until the write operation is completed (refer to Byte write timing).
* Page write
To maximise bus throughput, one technique is to allow the master to poll for an acknowledge signal after the start condition and the control byte for a write command have been sent. If the device is still busy implementing its write cycle, then no ACK will be returned. The master can send the next read/write command when the ACK signal has finally been received.
S e n d W r ite C o m m a n d
S e n d S to p C o n d itio n to In itia te W r ite C y c le S e n d S ta rt S e n d C o n tro l B y te w ith R /W = 0
The 32K EEPROM is capable of a 32-byte page write. A page write is initiated in the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges the receipt of the first data word, the microcontroller can transmit up to 31 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Page write timing).
(A C K = 0 )? Yes N e x t O p e r a tio n
No
Acknowledge Polling Flow
W r ite
S ta rt S D A L in e
S ta rt
S to p
D e v ic e A d d r e s s
A2A1A0
F ir s t W o r d A d d r e s s
S e c o n d W o rd A d d re s s
D a ta
ACK R /W
Byte Write Timing
W r ite S to p
ACK
ACK
ACK
D e v ic e A d d r e s s
A2A1A0
F ir s t W o r d A d d r e s s ( n ) S e c o n d W o r d A d d r e s s ( n )
D a ta (n )
D a ta (n + x )
S D A L in e
ACK R /W
ACK
ACK
ACK
ACK
N o t e : * = D o n 't c a r e b it s
Page Write Timing
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* Write protect * Random read
The HT24LC32 can be used as a serial ROM when the WP pin is connected to VCC . Programming will be in h ib it e d a n d t h e e n t i r e m e m o r y w i l l b e write-protected.
* Read operations
Read operations are initiated in the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read.
* Current address read
A random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the EEPROM. The microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller should respond with a no ACK signal (high) followed by a stop condition (refer to Random read timing).
* Sequential read
The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address remains valid between operations as long as the chip power is maintained. The address will roll over during read from the last byte of the last memory page to the first byte of the first page. The address will roll over during write from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but generates a following stop condition (refer to Current read timing).
Read S ta rt S D A L in e
W r ite
Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll over and the sequential read continues. The sequential read operation is terminated when the microcontroller does not respond with a zero but generates a following stop condition.
S to p
D e v ic e a d d r e s s A 2 A 1A 0
D a ta
Current Address Read Timing
ACK R /W
NoACK
Read
D e v ic e A d d r e s s
A2A1A0
1 s t, 2 n d W o rd A d d re s s (n )
S ta rt S D A L in e
S ta rt
S to p
D e v ic e A d d r e s s
A2A1A0
D a ta (n )
D u m m y W r ite N o t e : * = D o n 't c a r e b it s
ACK R /W
Random Read Timing
ACK
ACK
NoACK
Read
D e v ic e A d d re s s
S D A L in e
S to p
D a ta (n )
D a ta (n + 1 )
D a ta (n + 2 )
D a ta (n + x )
ACK R /W
ACK
ACK
NoACK
Sequential Read Timing
ACK
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Timing Diagrams
tF SCL tS SDA SDA OUT
U :S T A
tR tL tH
OW D :S T A
tH
IG H
tH
D :D A T
tS
U :D A T
tS tB
U :S T O
tS
P
tA
A
UF
V a lid
V a lid
SCL SDA 8 th b it W o rd n S to p C o n d itio n ACK tW
R
S ta rt C o n d itio n
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command.
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Package Information
8-pin DIP (300mil) Outline Dimensions
A B 1 8 5 4
H C D E F G
=
I
Symbol A B C D E F G H I a
Dimensions in mil Min. 355 240 125 125 16 50 3/4 295 335 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 375 260 135 145 20 70 3/4 315 375 15
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8-pin SOP (150mil) Outline Dimensions
A 1
8
5 B 4
C
C' G D E F
H
=
Symbol A B C C D E F G H a
Dimensions in mil Min. 228 149 14 189 53 3/4 4 22 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 244 157 20 197 69 3/4 10 28 12 10
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8-pin TSSOP Outline Dimensions
8
5 E1
1
4
D A e R 0 .1 0 (4 C O R N E R S ) B y A1 A2 C L
E
L1
G
Symbol A A1 A2 B C D E E1 e L L1 y q
Dimensions in mm Min. 1.05 0.05 0.95 3/4 0.11 2.9 6.2 4.3 3/4 0.5 0.9 3/4 0 Nom. 3/4 3/4 3/4 0.25 3/4 3/4 3/4 3/4 0.65 3/4 3/4 3/4 3/4 Max. 1.2 0.15 1.05 3/4 0.15 3.1 6.6 4.5 3/4 0.7 1.1 0.1 8
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Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SOP 8N Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301.0 621.5 13.0+0.5 -0.2 2.00.15 12.8+0.3 -0.2 18.20.2
TSSOP 8L Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 3301 621.5 13+0.5 -0.2 20.5 12.8+0.3 -0.2 18.20.2
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Carrier Tape Dimensions
P0 D
E F W C
P1
t
B0
D1
P
K0 A0
SOP 8N Symbol W P E F D D1 P0 P1 A0 B0 K0 t C TSSOP 8L Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 12+0.3 -0.1 80.1 1.750.1 5.50.5 1.5+0.1 1.5+0.1 40.1 20.1 70.1 3.60.1 1.60.1 0.30.013 9.3 Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 12.0+0.3 -0.1 8.00.1 1.750.1 5.50.1 1.550.1 1.5+0.25 4.00.1 2.00.1 6.40.1 5.200.1 2.10.1 0.30.05 9.3
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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